circuit note cn- 0187 circuits from the lab? reference circuits are engineered and tested for quick and easy system integration to help solve todays analog, mixed - signal, and rf design challenges. for more i nformation and/or support , visit www.analog.com/cn0187 . devices connected /referenced adl5502 450 mhz to 6 ghz crest factor detector ad7266 differential/single - ended input, dual, simultane ous sampling, 2 msps, 12 - bit, 3 - channel sar analog - to - digital converter ada4891 -4 low cost , quad , cmos, high speed, rail - to - rail amplifier adp121 1 50 ma, low qu iescent current, cmos linear regulator in 5 - lead tsot or 4 - ball wlcsp crest factor, peak, and rms rf power measurement circuit optimized for high speed, low power, and single 3 .3 v supply rev .0 circuits from the lab? circu its from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab en vironment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special , incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. evaluation and desig n support circuit evaluation boards cn - 0187 circuit evaluation board (eval - cn 0187 - sdp z) system demonstration platform (eval - s dp - cb1z) design and integration files schematics, layout files, bill of materials circuit function and benefits the circuit shown in figure 1 measure s peak and rms power at any rf frequency fro m 450 mhz to 6 ghz over a range of approximately 45 db. the measurement results are converted to differential signals in order to eliminate noise and are provided as digital codes at the output of a 12 - bit sar adc with serial interface and integrated refe rence. a simple two - point calibration is performed in the digital domain. u3-a u3-d u1 comm enbl va1 va2 vb1 vb2 d cap b d cap a 0.47f 27? 27? 27? agnd dgnd 10k? 10k? 0.47f 220? 220? 220? 442? 75? +3.3v c fltr * +3.3v 0.01f 0.01f rfin 0.01f 0.1f 1000pf +3.3v +3.3v avdd dvdd vdrive cs douta sclk adp121 adl5502 ad7266 +5.5v +3.3v 1f vin fltr vpos rfin vrms peak cntl vout en gnd 1f sdp board and support circuits note: u2 and u3 are ada4891-4 control (high reset; low peak hold) u5 u6 +1.25v +1.25v +2.5v * * * * *see text 8 4 1 2 3 7 6 5 u2-b u3-b 27? u2-d 10k? 10k? 0.47f 220? 220? 220? 442? +3.3v u3-d u3-a 0.47f +2.5v u2-a u2-c u3-c 09569-001 figure 1. high speed, low power, crest factor, peak, and rms power measurement system (simplified schematic: all connections and decoupling not shown)
cn- 0187 circuit note rev. 0| page 2 of 7 the adl5502 is a mean - responding (true rms ) power detector in combination with an envelope detector to accurately determine the crest factor (cf) of a modulated signal. it can be used in high frequency receiver and transmitter signal chains from 450 mhz to 6 ghz with envelope bandwidths over 10 mhz . the peak - hold function allows the capture of short peaks in the envelope with lower sampling rate adcs . total current consumption is only 3 ma @ 3 v. the ada4891 - 4 is a high speed , quad , cmos amplifier that offer s high performan ce at a low cost. current consumption is only 4.4 ma/amplifier at 3 v . the amplifier feature s true single - supply capability, with an input voltage range that extends 300 mv below the negative rail. the rail - to - rail output stage enables the output to swing to within 50 mv of each rail, ensuring maximum dynamic range. low distortion and fast settling time makes it ideal for this application. the ad7266 is a dual, 12 - bit, high speed, low power, successive approximation adc that operates from a single 2.7 v to 5.25 v power supply and features sampling rates up to 2 msps. the device contains two adcs, each preceded by a 3 - channel multiplexer, and a low noise, wide bandwidth track - and - hold amplifier that can handle input frequencies in excess of 30 mhz . current consumption is only 3 ma at 3 v. it also contains an internal 2.5 v reference. the circuit operates on a single +3 .3 v supp ly from the adp121 , a low q uiescent current, low dropout, linear regulator that operates from 2.3 v to 5.5 v and provides up to 150 ma of output current. the low 135 mv dropout voltage at 150 ma load improves effici ency and allows operation over a wide input voltage range. the low 30 a of quiescent current at full load makes the adp121 ideal for battery - operated portable equipment. the adp121 is available in output voltages ranging from 1.2 v to 3.3 v. the parts ar e optimized for stable operation with small 1 f ceramic output capacitors. the adp121 delivers good transient performance with minimal board area. short - circuit protection and thermal overload protection circuits prevent damage in adverse conditions. the adp121 is available in tiny 5 - lead tsot and 4 - ball , 0.4 mm pitch halide - free wlcsp packages and utilizes the smallest footprint solution to meet a variety of portable applications. circuit description the rf signal being measured is applied to the adl550 2. a single 75 termination resistor at the rf input in parallel with the input impedance of the adl5502 provides a broadband match of 50 . more precise resistive o r reactive matches can be applied for narrow frequency band use (see the rf input interfacing section o f the adl5502 data s heet). the internal filter capacitor of the adl5502 provides averaging in the square domain but leaves some residual ac on the output. signals with high peak - to - average ratios, such as w - cdma or cdma2000, can produce ac residual levels on the adl5502 vrms dc output. to reduce the effects of these low frequency components in the waveforms, some additional filtering is required. the internal square - domain filter capacitance of the adl5502 can be augmented by connecting a c fltr capacitor b etween pin 1 (fltr) and pin 2 (vpos). the ac residual can be reduced further by adding capacitance to the vrms output . the combination of the internal 100 output resistance and the added output capacitance produce s a low - pass filter to reduce output ripp le of the vrms output (see the selecting the square - domain filter and output low - pass filter section of the adl5502 data s heet for more details). to measure the peak of a waveform, the control line (cntl) must be temporally set to a logic high (reset mode for >1 s) and then set back to a logic low (peak - hold mode). this allows the adl5502 to be initialized to a known state. when setting the device to measure peak, peak - hold mode should be toggled for a period in which the input rms power and crest factor ( cf ) is not likely to change. if the adl5502 is in peak - hold mode and the cf changes from high to low or the input power changes from high to low, a faulty peak measurement is reported. the adl5502 simply keeps reporting the highest peak that occurred when the peak - hold mode was activated and the input power or the cf was high. unless cntl is reset, the peak output does not reflect the new peak in the signal. the adl5502 is capable of sourcing a vrms output current of approximately 3 ma. the output current i s sourced through the on - chip, 100 series resistor; therefore, any load resistor forms a voltage divider with this on - chip resistance. it is recommended that the adl5502 vrms output drive high resistive loads to preserve output swing. if an application r equires driving a low resistance load (as well as in cases where increasing the nominal conversion gain is desired), a buffering circuit is necessary. the peak output is designed to drive 2 pf loads. it is recommended that the adl5502 peak output drive low capacitive loads to achieve a full output response time. the effects of larger capacitive loads are particularly visible when tracking envelopes during the falling transitions. when the envelope is in a fall transition, the load capacitor discharges throu g h the on - chip load resistance of 1.9 k. if the larger capacitive load is unavoidable, the additional capacitance can be counteracted by putting a shunt resistor to ground on the peak output to allow for fast discharge. such a shunt resistor also makes the adl5502 run higher current, and it should not be lower than 500 .
circuit note cn- 0187 rev. 0| page 3 of 7 typical measured performance characteristics of the circuit are presented in figure 2 through figure 5 . 0.01 0.1 1 10 ?25 ?20 ?15 ?10 ?5 0 5 10 15 output (v) input (dbm) 450mhz 900mhz 1900mhz 2350mhz 2600mhz 09569-002 figure 2. measured vrms output vs. input level (log scale) , 450 mhz, 900 mhz, 1 900 mhz, 2350 mhz, 2600 mhz , supply +3. 3 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 output (v) input (v rms) 450mhz 900mhz 1900mhz 2350mhz 2600mhz 09569-003 figure 3. measured vrms output vs. input level (linear scale), 450 mhz, 900 mhz, 1900 mhz, 2350 mhz, 2600 mhz, supply +3. 3 v 0.01 0.1 1 10 ?25 ?20 ?15 ?10 ?5 0 5 10 15 output (v) input (dbm) 450mhz 900mhz 1900mhz 2350mhz 2600mhz 09569-004 figure 4 . measured peak output vs. input level (log scale) , 450 mhz, 900 mhz, 1900 mhz, 2350 mhz, 2600 mhz, supply +3. 3 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 output (v) input (v rms) 450mhz 900mhz 1900mhz 2350mhz 2600mhz 09569-005 figure 5. measured peak output vs. input level (linear scale), 450 mhz, 900 mhz, 1900 mhz, 2350 mhz, 2600 mhz, supply +3. 3 v the turn - on time and pulse response is strongly influenced by the size of the s quare - domain filter (c fltr ) and output shunt capacitor connected to the vrms output . figure 6 (taken from the adl5502 data sheet) shows a plot of the output response to an rf pulse on the rfin pin, with a 0.1 f output filter capacitor and no square - domain filter capacitor (c fltr ) . the falling edge is particularly dependent on the output shunt capacitance . vrms (250mv/div) 1ms/div 70mv rms 160mv rms 250mv rms 400mv rms rf input vrms pulsed rfin 09569-053 figure 6. output response to various rf input pulse levels, supply3 v, 900 mhz frequency, square - domain filter open, output filter 0.1 f to improv e the falling edge of the enable and pulse responses, a resistor can be placed in parallel with the output shunt capacitor. the added resistance helps to discharge the output filter capacitor. although this method reduces the power - off time, the added loa d resistor also attenuates the output (see the output drive capability and buffering section of the adl5502 data s heet ). figure 7 (taken from the adl5502 data sheet) shows the improvement obtained by adding a parallel 1 k ? resistor.
cn- 0187 circuit note rev. 0| page 4 of 7 vrms (250mv/div) 1ms/div 70mv rms 160mv rms 250mv rms 400mv rms rf input vrms pulsed rfin 09569-054 figure 7. output response to various rf input pulse levels, supply 3 v, 900 mhz frequency, square - domain filter open, output filter 0.1 f with parallel 1 k the rms and peak outputs of the adl5502 pass through unity gain buffers that drive cross - coupled stages for converting the single - ended outputs to differential signals. the internal +2.5 v reference of the ad7266 (via the d cap a and d cap b pins) passes through a nother unity gain buffer and a voltage divider. this sets the common - mod e voltage of the network to +1.25 v . the ad7266 achieves simultaneous samples of the rms and peak outputs and transfers the data within a 1 s response time. the data is provided on a single serial data line. because slope and intercept vary from device to device, board - level calibration must be performed to achieve high accuracy. in general, calibration is performed by applying two input power levels to the adl5502 and measuring the corresponding output voltages. the calibration points are generally chosen to be within the linear operating range of the device. the best - fit line is characterized by calculating the conversion gain (or slope) and intercept using the following equations: gain = ( v vrms2 ? v vrms1 )/( v in2 ? v in1 ) ( 1 ) intercept = v vrms1 ? ( gain v in1 ) ( 2 ) where: v in is the rms input voltage to rfin. v vrms is the voltage output at vrms. once gain and intercept are calculated, an equation can be written that allows calculation of an (unknown) input power based on the measured output voltage. v in = ( v vrms ? intercept )/ gain (3) for an ideal (known) input power, the law conformance error of the measured data can be calculated as C log 20 (db) ? ? ? ? ? ? ? ? = in, ideal ured vrms, meas v gain intercept v error ( 4 ) figure 8 and figure 9 show plot s of the vrms and peak error at 25c, the temperature at which the adl5502 is calibrated. note that the error is not zero; this is because the adl5502 does not perfectly follow the ideal linear equation, even within its operating region. the er ror at the calibration points is, however, equal to zero by definition. ?3 ?2 ?1 0 1 2 3 error (db) input (dbm) ?25 ?20 ?15 ?10 ?5 0 5 10 15 450mhz 900mhz 1900mhz 2350mhz 2600mhz 09569-008 figure 8. measured vrms linearity error vs. input level, 450 mhz , 900 mhz, 1900 mhz, 2350 mhz, 2600 mhz, supply +3. 3 v ?3 ?2 ?1 0 1 2 3 error (db) input (dbm) ?25 ?20 ?15 ?10 ?5 0 5 10 15 450mhz 900mhz 1900mhz 2350mhz 2600mhz 09569-009 figure 9. measured peak linearity error vs. input level, 450 mhz, 900 mhz, 1900 mhz, 2350 mhz, 2600 mhz, supply +3. 3 v when the characteristics (slope and intercept) of the vrms and peak outputs are known, the calibration for the cf calculation is complete. a three - stage process must be taken to measure and ca lculate the crest factor of any waveform. first, the unknown signal must be applied to the rf input , and the corresponding vrms level is measured. this level is indicate d in figure 10 as v vrms - unknown . the rf input, v in , is calculated using v vrms - unknown and equation 3.
circuit note cn- 0187 rev. 0| page 5 of 7 input (v rms) output (v) vrms of unknown waveform (result independent of waveform) peak of cw, cf = 0db peak of unknown waveform 0 v in v vrms-unknown v peak-cw v peak-unknown 1 2 3 09569-057 figure 10 . procedure for crest factor calculation next, the cw reference level of peak, v peak - cw , is calculated using v in (that is, the output voltage that would be seen if the incoming waveform was a cw signal). v peak - cw = ( v in gain peak ) + intercept peak (5) finally, the actual level of peak, v peak - unknown , is measured and the cf can be calculated as cf = 20 log 10 ( v peak - unknown / v peak - cw ) (6) where v peak - cw is used as a reference point to compare v peak - unknown . if both v peak values are equal, then the cf is 0 db, as shown in figure 11 with the cw signal (taken from the adl5502 data sheet) . across the dynamic range, the calculated cf hovers about the 0 db line. likewise, for complex waveforms of 3 db, 6 db, and 9 db cfs, t he calculations accurately hover about the corresponding cf levels. ?1 0 1 2 3 4 5 6 7 8 9 10 input (dbm) crest factor (db) ?25 ?20 ?15 ?10 ?5 0 5 10 15 8-tone waveform, 9db cf 4-tone waveform, 6db cf 2-tone waveform, 3db cf cw, 0db cf 09569-058 figure 11 . reported crest factor of various waveforms ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 ?25 ?15 ?5 5 15 crest f ac t or (db) input (dbm) 450mhz 900mhz 1900mhz 2350mhz 2600mhz 09569-012 figure 12. measured crest factor of cw signals vs. input level, 450 mhz, 900 mhz, 1900 mhz, 2350 mhz, 2600 mhz, su pply +3. 3 v the performance of this or any high speed circuit is highly dependent on proper pcb layout. this includes, but is not limited to , power supply bypassing, controlled impedance lines (where required) , component placement, signal routing, and pow er and ground planes. ( see mt - 031 tutorial , mt - 101 tutorial , and article, a practical guide to high - speed printed - circu it - board layout , for more detailed information regarding pcb layout.) a complete design support package for this circuit note can be found at http://www.analog.com/cn0187 - designsupport . c ommon v ariations for applications that require less rf detection range, the ad8363 rms detector can be used. the ad8363 has a detection range of 50 db and operates at frequencies up to 6 ghz. for non - rms detection app lications, the ad8317 / ad831 8 / ad831 9 or adl5513 can be used. these devic es offer varying detection range s and have varying input frequency ranges up to 10 ghz (see cn - 0150 for more details). circuit evaluation a nd test t his circuit uses the eval - cn 0 1 87- sdpz circuit board and the e va l - sdp - cb1z system demonstration platform (sdp) evaluation board. the two boards have 120 - pin mating connectors, allowing for the quick setup and evaluation of the circuits performance. the eval - cn 0 1 87- sdpz board contains the circuit to be evaluated, as described in this note, and the sdp evaluation board is used with the cn01 87 evaluation software to capture the data from the eval - cn 0 1 87- sdpz circuit board.
cn- 0187 circuit note rev. 0| page 6 of 7 equipment needed ? pc with a usb p ort and windows? xp or windows vista? ( 32- bit), or windows? 7 ( 32 - bit) ? e va l - cn01 87- sdpz circuit e valuation b oard ? e va l - sdp - cb1z sdp e valuation b oard ? cn01 87 e valuati on s oftware ? power supply: +6 v, or +6 v wall wart ? rf signal source ? coaxial rf cable with sma connectors getting started load the e valuation s oftware by placing the cn0 1 87 evaluation software d isc in the cd drive of the pc. using "my c omputer, " locate the drive that co ntains the evaluation software disc and open the readme file. follow the instructions contained in the r eadme file for installing and using the evaluation software. functional block diagram see f igure 1 of this circuit note for the circuit block diagram, and the eval - cn 0187- sdpz - sch pdf file for the circuit schematics. this file is contained in the cn0187 design support package . setup connect the 120 - pin connector on the eval - cn 0 1 87- sdpz circuit board to the connector marked con a on the e va l - sdp - cb1z evaluation (sdp) board. nylon hardware should be used to firmly secure the two bo ards, using the holes provided at the ends of the 120 - pin connectors. using an appropriate rf cable, connect the rf signal source to the e va l - cn 0 1 87- sdpz board via the sma rf input connector. with power to the supply off, connect a + 6 v pow er supply to the pins marked + 6 v and gnd on the board. if available , a + 6 v " wall wart " can be connected to the barrel jack connector on the b oard and used in place of the + 6 v power supply. connect the usb cable supplied with the sdp board to the usb port on the pc. note : d o no t connect the usb cable to the m ini usb connector on the sdp board at this time . test apply power to the + 6 v supply (or wall wart ) connected to e va l - cn 0 1 87- sdpz circuit board. launch the e valuation software and connect the usb cable from the pc to the usb m ini - connector on the sdp board. the software will be able to communicate to the sdp board if the analog devices system development platform driver is listed in the device manager. once usb communications are established, the sdp board can n ow be used to send, receive, and capture serial data from the e va l - cn 0 1 87- sdpz board. the data in this circuit note w ere generated using a rohde & schwarz smt - 03 rf signal source and an agilent e3631a power supply. the signal source was set to the freque ncies indicated in the graphs, and the input power was stepped and data recorded in 1 db increments. information and details regarding how to use the evaluation software for data capture can be found in the cn 0 1 87 evaluation software read m e file. informat ion regarding the sdp board can be found in the sdp user guide . learn more cn0187 design support package: http://www.analog.com/cn0187 - d esignsupport sdp user guide ardizzoni, john. a practical guide to high - speed printed - circuit - board layout , analog dialogue 39 - 09, september 2005. cn - 0150 circuit note, software - calibrated, 1 mhz to 8 ghz, 70 db rf power measurement system using the ad8318 logarithmic detector , analog devices. mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd , analog devices. mt - 073 tutorial, high speed variable gain amplifiers (vgas) , analog devices. mt - 077 tutorial, log amp basics , analog devices. mt - 078 tutorial, high speed log amps , analog devices. mt - 081 tutorial, rms - to - dc converters , analog devices. mt - 101 tutorial, decoupling techniques , analog devices. whitlow, dana. design and operation of automatic gain control loops for receivers in modern c ommunications systems . chapter 8 . analog devices wireless seminar. 2006. data sheets and evaluation boards cn - 0187 circuit evaluation board (eval - cn0187 - sdpz) system demonstration platform (eval - sdp - cb1z) adl5502 data sheet adl5502 evaluation board ad7266 data sheet ad7266 evaluation board ada4891 data sheet
circuit note cn- 0187 rev. 0| page 7 of 7 revision history 4/11 rev ision 0 : initial version (continued from first page) circuits from the lab circuits are inten ded only for use with analog devices products and are the intellectual property of analog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the circuits from the lab circuits . information furnished by analog devices is believed to be accurate and reliable. however, "circuits from the lab" are suppl ied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability , noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for an y infringements of patents or other rights of third parties that may result from their use. analog devices reserves the right to change any circuits from the lab circuits at any time without notice but is under no obligation to do so. ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn09569 - 0 - 4/11(0)
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